1. Field of the Invention
The present invention relates to Error Correction and Constraint Coding and, in particular, to a system and method for Reverse Error Correction Coding.
2. Background Art
Error Correction coding/decoding (ECC) and Constraint encoding/decoding, such as Run Length Limited encoding/decoding (i.e., RLL) and Variable Rate Randomizer encoding/decoding (VR2), are generally implemented in conventional data communication systems to provide increased data reliability during data transfer over a noise inducing medium (e.g., to/from a magnetic media, etc.).
ECC encoding generally involves appending data, such as one or more parity bits, to a source data stream presented to an ECC encoder. The appended data may provide data redundancy such that the source data may be recovered in the event the noise inducing medium introduces one or more errors into the source data.
In contrast, Constraint encoding is generally implemented to insure, inter alia, that adequate timing information is present in a data stream. The timing information may be used by a tracking mechanism, such as a clock, to synchronize one or more data handling elements (e.g., a read and/or write element) with the data stream such that intersymbol interference may be reduced. In general, timing information may be deemed adequate when the resulting data stream (i.e., Constraint encoded data stream) satisfies a predetermined k-constraint. For example, when the predetermined k-constraint is (0,9), the timing information may be deemed adequate when the resulting data stream has no more than nine 0-bits between consecutive 1-bits. Satisfying a predetermined k-constraint generally provides adequate timing information in systems wherein a timing mark is generally coincident with a high signal state (e.g., coincident with a 1-bit). An example of such a system may be a magnetic media drive wherein a write mechanism of the drive generates a new magnetic mark coincident with the occurrence of a high signal state in the written data stream. The magnetic marks may synchronize a clock of the drive such that a subsequent read element may be synchronized with the written data stream.
FIG. 1 illustrates a conventional system 10 for communicating data. Because an ECC encoder generally appends (i.e., adds, inserts) additional data bits to a data stream, the system 10 generally implements an ECC encoder 12 prior to a Constraint encoder 14. Accordingly, the data bits inserted by the ECC encoder 12 are available at the subsequent Constraint encoder 14 for processing such that the resulting (i.e., processed) data stream, as a whole, satisfies a predetermined k-constraint. As illustrated in FIG. 1, the decoding process is generally the reverse of the encoding process and may include a Constraint decoder 16 receiving a previously encoded data stream and passing a Constraint decoded data stream to a subsequent ECC decoder 18.
Due to the non-linear nature of RLL, VR2 and other Constraint encoding/decoding algorithms, an error introduced into an encoded data stream may be propagated upon subsequent Constraint decoding (e.g., via Constraint decoder 16). Such propagation may increase the quantity and/or severity of errors such that the subsequent ECC decoder 18 is unable to successfully correct the errors.
Furthermore, many Constraint coding algorithms, such as RLL and VR2, are unable to output “soft information” (i.e., probability information having a value between 0 and 1). Accordingly, the system 10 is not suitable for implementing soft ECC decoding, such as a Low-Density Parity-Check decoder (i.e., LDPC).
One attempt to address the shortfalls of the system 10 may be referred to as Reverse ECC. In Reverse ECC, a data stream is generally subjected to Constraint encoding prior to ECC encoding. Accordingly, the encoded data stream is generally subjected to ECC decoding prior to Constraint decoding. Such a system may reduce error propagation and/or allow for implementation of soft ECC decoding. However, additional Constraint encoding (e.g., a second RLL encoding) must be performed on the data bits amended by the ECC encoder as the amended bits may otherwise cause the resulting (i.e., encoded) data stream to violate the predetermined k-constraint.
An attempt to address the shortfalls of Reverse ECC is disclosed in United States Patent Publication no. 2005/01385522 to Silvus (i.e., Silvus). Silvus teaches a system and method for implementing Reverse ECC without requiring a second RLL code. Silvus appends a “seed” to the RLL encoded data. The “seed” alters the parity values of the ECC so that they meet an RLL constraint. However, Silvus requires the determination and insertion of an appropriate “seed” (i.e., any symbol, bit, word or other data inserted in to the channel data which is selected to meet a desired RLL constant). Determination of an appropriate seed may require several iterations.
Accordingly, it would be desirable to have a system and a method for implementing Reverse ECC to reduce error propagation and/or provide “soft information” Error Correction Coding wherein the output of the ECC encoder may be made to satisfy a predetermined k-constraint without requiring a second Constraint encoding and/or the use of an iterative seeding process.